Design of semiconductor integrated circuits has moved from an essentially graphic process to a textual programming language process. Electronic design automation (EDA) is a collection of software tools used to both design and analyze integrated circuits. Design flows for chip design include logic synthesis, placement, routing, and analysis. Design flow steps can be performed in order, or some steps may be integrated to efficiently create an optimized circuit design. Logic synthesis is the process of expressing each functional circuit design requirement into a representation of physical logic circuits or gates. The logic circuits are summed up in a netlist for the design. Placement is the process where all components of a netlist are physically placed on a map of the chip area while optimizing wire length, longest path, congestion, and power consumption. Routing is the process where all the placed components are wired together. At this point, a rough physical design is complete, and the design flow proceeds to analysis.
Analysis of circuit designs may include simulation, physical verification, and static timing analysis (STA). Simulation includes methods, such as transistor simulation, logic simulation, or behavioral simulation. Physical verification is the process of determining the manufacturability of an integrated circuit design. Static timing analysis (STA) is a method for computing the timing of a digital circuit design, particularly looking for hold time violations and setup time violations. An early mode, or hold time violation occurs when data arrives too early to be properly latched into a storage element. A late mode, or setup time violation occurs when data arrives too late. Based on the timing analysis, extra delay books, delay inverters or buffers are added to the digital circuit design to slow down signals that arrive too early. Delay books or delay inverters take up valuable area in the chip design which may already be congested.